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Hybrid Wallace Tree Multiplier Using 4:2 Compressor in Carry Save Addition Mode

The multiplier is one of the important elements in most of the digital processing system such as FIR filters, digital signal processors, and microprocessors etc. The speed of a system depends upon how a faster an arithmetic operations are performed within the structure for which mostly multiplication should be carried out at a faster rate which thus improves the system performance. The two important parameters of a multiplier are its area and speed that are inversely proportional. Multipliers are of great significance in today’s Digital Signal processing applications like DFT, IDFT, FFT, IFFT, and ALU in Microprocessor.  Wallace tree multiplier along with a Ripple Carry adder is hybridized and formed a hybridized multiplier which delivers high-speed computation along with the reduction in power consumption. Here, Wallace tree multiplier is used to increase the speed of addition and a Ripple Carry Adder is used for final accumulation. This hybrid multiplier produces better results in terms of speed and power than the conventional designs. The proposed circuit is designed and the results are discussed in the paper. This proposed work is evaluated in the basic area, power, and delay.

Published by: Ankur Katkar, Sunil Kuntawar, Vijay Roy

Author: Ankur Katkar

Paper ID: V4I1-1204

Paper Status: published

Published: January 15, 2018

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Review Paper

Catercam- A Sliding Camera Mechanism Using Gimbal Assembly

In the current era of 21st century technocrats focus on building more efficient, compact, power efficient and cheap substitute for technology presently used. A CCTV camera is a widely used product for surveillance, but many times just to cover a small area it is required to have more than one camera at the same place viz. a parking space which requires 180 degrees coverage or a ‘U’ shaped road requires at least two cameras to have a complete footage of the sector area. Similarly for recording a remote area which is seldom used. Furthermore, in some areas cameras are installed to work for just a small amount of time for viz. CCTV in the classroom to check how many students were present in the class. Adapting this technology will reduce the number of camera units used in a particular area, work of maintenance department and moreover a huge amount of energy is saved which can be utilized for villages where people face scarcity of electrical energy.

Published by: Kashyap Kirtikar, Shubham Ghodke, Atharva Shirode, Vismita Nagrale

Author: Kashyap Kirtikar

Paper ID: V4I1-1202

Paper Status: published

Published: January 15, 2018

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Review Paper

Making of Two South Korean Chaebols: Samsung and Hyundai

The management system of South Korean companies has been influenced by their traditional beliefs and values of Confucianism bought up by Chinese in the 15th century. Yet, this Confucius management style was shifted to western style after the Asian financial crisis of 1997. Few prominent conglomerate led to the growth of South Korea from developing the country to one the wealthiest country in the world. This paper aims to evaluate this management transition in two major South Korean companies i.e. Samsung and Hyundai. This paper shows how management system changed in South Korea in five main major vectors: (A) Decision-making style, (B) shift to corporate governance, (c) change in performance management, (D) corporate social responsibility, (E) government intervention and support

Published by: Hardik Jain , Shantanu Kaushik

Author: Hardik Jain

Paper ID: V4I1-1210

Paper Status: published

Published: January 15, 2018

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Research Paper

VHDL Implementation of 32-Bit Microprocessor

The digital design is a very broad field. Its applications can be found in our daily life such as in laptops, calculators, cameras etc. The VHDL has become an essential tool for designers in the world of digital design[1]. This paper presents the VHDL implementation of a 32-bit microprocessor. The structural VHDL model of the microprocessor is designed to perform 16 operations which include both logical and arithmetic operation. Here the microprocessor is divided into various sub-modules and each of them was programmed using VHDL. The VHDL implementation and functionality test of the 32-bit microprocessor are done by using the Xilinx tool.

Published by: Kusumam Joseph, Merlyn Mariyam Varghese

Author: Kusumam Joseph

Paper ID: V4I1-1201

Paper Status: published

Published: January 13, 2018

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Survey Report

A Survey on Sparsity Based Single Image Super Resolution of Colour Images

There are several methods for improving the resolution of images. The usual approach is by sparsely representing patches in a low-resolution input image via a dictionary of an example low-resolution patches and then using the coefficients of this representation to generate the high-resolution output via an analogous high-resolution dictionary. However, most existing methods focus on luminance channel information only and neglect the colour channels. The present method achieves sparsity-based super resolution by considering multiple colour channels also along with luminance channel Information. Edge similarities among RGB colour bands are used as cross channel correlation constraints. A dictionary learning method specifically to learn colour dictionaries that encourage edge similarities is also used. The advantages of this method are demonstrated both visually and quantitatively using image quality metrics.

Published by: Helena Thomas, Anitha R

Author: Helena Thomas

Paper ID: V4I1-1197

Paper Status: published

Published: January 13, 2018

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Research Paper

Layout Design of 5 Transistor D Flip Flop for Power and Area Reduction and Performance Comparison in Different Scaling Technologies

Due to increase in demand for portable devices low power dissipation is an essential need for device design. Due to advances in low power applications low power digital CMOS has become more important, and the process technology has been advanced. In this paper, an SET D flip-flop with 5 transistors is proposed. This D flip-flop has been implemented using different scaling technologies such as 180 nm, 90 nm, 70 nm and 50 nm. Both power dissipation as well as area has been compared. The layout of the 5 transistor D FF is designed. It has been observed from simulation result that the fully custom design has shown 39% reduction in area and 37% reduction in power as compared to fully automatic design. This design technique achieves lowest power consumption with reduced transistor count. It can be used in applications like buffers, registers, digital clocks etc.

Published by: Shermina M. Meera, Shahanaz M. Meera, Nishi G. Nampoothiri

Author: Shermina M. Meera

Paper ID: V4I1-1192

Paper Status: published

Published: January 13, 2018

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