This paper is published in Volume-4, Issue-1, 2018
Area
VLSI
Author
Shermina M. Meera, Shahanaz M. Meera, Nishi G. Nampoothiri
Org/Univ
Musaliar College of Engineering & Technology, Pathanamthitta, Kerala, India
Pub. Date
13 January, 2018
Paper ID
V4I1-1192
Publisher
Keywords
D Flip Flop, CMOS, Low Power VLSI, Power Consumption, Scaling Technologies

Citationsacebook

IEEE
Shermina M. Meera, Shahanaz M. Meera, Nishi G. Nampoothiri. Layout Design of 5 Transistor D Flip Flop for Power and Area Reduction and Performance Comparison in Different Scaling Technologies, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Shermina M. Meera, Shahanaz M. Meera, Nishi G. Nampoothiri (2018). Layout Design of 5 Transistor D Flip Flop for Power and Area Reduction and Performance Comparison in Different Scaling Technologies. International Journal of Advance Research, Ideas and Innovations in Technology, 4(1) www.IJARIIT.com.

MLA
Shermina M. Meera, Shahanaz M. Meera, Nishi G. Nampoothiri. "Layout Design of 5 Transistor D Flip Flop for Power and Area Reduction and Performance Comparison in Different Scaling Technologies." International Journal of Advance Research, Ideas and Innovations in Technology 4.1 (2018). www.IJARIIT.com.

Abstract

Due to increase in demand for portable devices low power dissipation is an essential need for device design. Due to advances in low power applications low power digital CMOS has become more important, and the process technology has been advanced. In this paper, an SET D flip-flop with 5 transistors is proposed. This D flip-flop has been implemented using different scaling technologies such as 180 nm, 90 nm, 70 nm and 50 nm. Both power dissipation as well as area has been compared. The layout of the 5 transistor D FF is designed. It has been observed from simulation result that the fully custom design has shown 39% reduction in area and 37% reduction in power as compared to fully automatic design. This design technique achieves lowest power consumption with reduced transistor count. It can be used in applications like buffers, registers, digital clocks etc.