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Review on big data: Prediction techniques and analytics architecture for E-agriculture

Big data is a very new and important trend in agriculture domain. People now realize the importance of Big Data in E-Agriculture. Big data analytics is a very tough thing in the agriculture field. However, how to use big data analytics in agriculture field to improve the productivity in practices. Purpose of this E-Agriculture to reduce technological gap between rural communities and share information via recommendations and decision support system. Apache Spark is a distributed memory-based computing framework which is naturally suitable for machine learning. Hadoop, the spark has the better way of functionality and ability of computing learning. In this paper, analyze spark framework with basic concept means spark’s primary framework this paper proposes an architecture for managing big data in the agriculture area. The main advantage of this method is managing massive dataset which is already existing. This technique is faster than any other traditional one.

Published by: Patel Jaydeep Pravinbhai, Ashutosh Abhangi

Author: Patel Jaydeep Pravinbhai

Paper ID: V4I3-1251

Paper Status: published

Published: May 5, 2018

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Research Paper

Prediction model of crop yield for food crop grown above ground level through big data analytics

Agriculture is believed to be as the backbone of Indian economic system. For the past few decades, agriculture field has seen lots of technological changes to improve better productivity. Day by day the population is increasing leading to increasing demand for resources but the amount of resources required has been reducing and falling down. Therefore, there has been extensive endeavors to create imaginative and technological advances methodologies for manageable harvest generation. Using prediction methods, farmers can enhance the productivity of crops. These strategies are utilized to find the required number of crops, seeds, moistness, water level and other supplements. Since prediction refers to a statement about an uncertain event, hence modeling the prediction would a good solution to adopt. Predictive modeling uses statistics to predict outcomes. Quantifying the yield is essential to optimize policies to ensure food security. This paper aims at providing a new method to predict the crop yield of food crops grown above the ground level based on big-data analysis technology, which differs with traditional methods in the structure of handling data and in the means of modeling. Firstly, the method can make full use of the existing massive agriculture relevant datasets and can be still utilized with the volume of data growing rapidly, due to big-data friendly processing structure. Secondly, the "nearest neighbors"modeling, which employs results gained from the former data processing structure.

Published by: Varisha Ashraf, Ankit Jain, Manjunath C. R, Sahana Shetty

Author: Varisha Ashraf

Paper ID: V4I3-1263

Paper Status: published

Published: May 5, 2018

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Research Paper

Efficient implementation of full adder and multiplier for power analysis in CMOS technology

In recent days, the real-time application and fast arithmetic operations require highly efficient arithmetic hardware architecture to improve the system performances. The adder plays a vital role in digital circuits, the earlier hardware architecture using conventional CMOS and transmission logic gate based full adder design. Moreover, the techniques using more number of transistors and consume larger power and delay so we proposed the techniques pass-transistor logic and transmission gate based hybrid pass logic. The hybrid technique is used to reduce the number of the transistor, so the delay and power consumption will be reduced when compared with the earlier techniques. The proposed technique design was implemented using 16 transistors in 180nm CMOS technology and it consumes 8.2075nW power and the delay reduced to 5.0146ns. For further improving the power and delay will be minimized using analog multiplier technique which is implemented in 180nm CMOS technology and it consumes 3.2993 MW power and 1.2884 ms.

Published by: Kaleeswari. S, Saranya. K

Author: Kaleeswari. S

Paper ID: V4I3-1258

Paper Status: published

Published: May 5, 2018

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Research Paper

Implementation of pull-up/pull-down network for energy optimization in full adder circuit

Nowadays the requirements of energy-optimized low power circuits in higher-end applications such as communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power circuits but the static power dissipation needs to improved such kind of circuits. The conventional topology has been implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to reduce the static power dissipation in full adder is used to improve the operating speed of each individual. For further improving the operating speed of the full adder is implemented with various gating technique like Body Biased Drain Gating, Body Biased Power Gating, Body Biased DHPH, and Body Biased DHPF those techniques are analyzed and its power and delay is obtained.

Published by: P. Aarthi, R. Suresh Kumar

Author: P. Aarthi

Paper ID: V4I3-1257

Paper Status: published

Published: May 5, 2018

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Dissertations

Knee extensor strengthening versus hip and ankle in anterior knee pain

Anterior knee pain or patellofemoral pain syndrome is concerned of softening of articular cartilage between femur and patella causing erosion of articular cartilage mild to moderate concentric muscle contraction wasting increased “Q” angle postural change, Physiotherapy including hip and ankle strengthening and knee strengthening postural correction can improve symptoms. Purpose: The purpose of the study is to know about which of this groups are more effecting in treating the anterior knee pain effectively group “a” to strengthen hip and ankle postural correction group “b” knee strengthening patellar mobilization. Methods : 30 patients are randomly selected with anterior knee pain .the study include 2 groups group 1 receives knee strengthening patellar gliding warm water fermentation group 2 receives hip and ankle strengthening with postural correction both groups .the outcome includes visual analogue scale, Kujala scale for knee disability and knee outcome survey scale for activities of daily living . Results: There was a significant decrease in pain with hip and ankle strengthening postural correction (hip abductors, external rotator, extensors, ankle supinators, strengthening, stretching of hip adductors, internal rotators, ankle pronators) postural correction than the knee strengthening patellar mobilization (P-0.000<0.05). Hip and ankle strengthening postural correction were decreased in VAS and improving in “Q” angle. Knee extensor and patellar mobilization have not such effective treatment for patella femoral or anterior knee pain. Conclusion: Patella femoral or anterior knee pain relieves with hip and ankle strengthening with postural correction (hip abductors, external rotator, extensors, ankle supinators, strengthening, stretching of hip adductors, internal rotators, ankle pronators) postural correction.    

Published by: S. Pavan Kumar, J Sravana Kumar, Lalith Mohan

Author: S. Pavan Kumar

Paper ID: V4I2-1281

Paper Status: published

Published: May 3, 2018

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Research Paper

Design and analysis of VLSI circuit’s speed using CNFET technology

This paper presents the difference between the CNFET and CMOS technologies by using the design of an efficient 8×8 Vedic multiplier with Urdhva-Tiryagbhyam sutra. A carbon nanotube field-effect transistor (CNFET) uses either a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. CNFETs show different characteristics compared to MOSFETs in their performances. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This reduces the size of the chip but also cost and delay to a great extent. Here the comparison of CMOS technique with the proposed CNFET technique in terms of speed, power consumption, number of transistors, delay takes place.

Published by: Shaik Suhana, Yarasi Thejsawini, P. Madhavi

Author: Shaik Suhana

Paper ID: V4I3-1219

Paper Status: published

Published: May 3, 2018

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