This paper is published in Volume-3, Issue-3, 2017
Area
Low Power
Author
Roopali
Co-authors
Uma Nirmal
Org/Univ
Mody University, India
Pub. Date
10 May, 2017
Paper ID
V3I3-1148
Publisher
Keywords
Adiabatic Logic, 2pascl, Low Power, Full Adder, Static Energy Recovery Logic.

Citationsacebook

IEEE
Roopali, Uma Nirmal. Low Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Roopali, Uma Nirmal (2017). Low Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic. International Journal of Advance Research, Ideas and Innovations in Technology, 3(3) www.IJARIIT.com.

MLA
Roopali, Uma Nirmal. "Low Power Full Adder Circuit Design Using Two Phase Adiabatic Static CMOS Logic." International Journal of Advance Research, Ideas and Innovations in Technology 3.3 (2017). www.IJARIIT.com.

Abstract

Adiabatic logic is used to minimize the energy loss during operation of the circuit. Using two phase adiabatic static CMOS logic (2PASCL) the power consumption can be reduced. This paper compare the power consumption of Static Energy Recovery Full Adder(SERF) and the proposed full adder using two phase adiabatic static CMOS logic(2PASCL). The average power consumption of proposed full adder is 4.8pW which is very less in comparative study with SERF. The result of this work focuses on the reduction of power consumption with the scaling down technology.
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