In this proposed work we are applying valuable power gating schemes to FinFET based Schmitt trigger to enhance its performance by reducing the leakage current in standby mode (off-state mode). The power gating schemes like Sleep Transistor approach and Multi-Threshold CMOS (MTCMOS) and Double-Threshold CMOS(DTCMOS) have been analysed and simulated which shows the tremendous reduction in the leakage current thus increasing the stability of the design. In this paper, different consecutive designs of PULL-UP and PULL-DOWN networks of NMOS and PMOS are applied to FinFET based Schmitt trigger one after another. Due to this treatment of PULL-UP and PULL-DOWN network, controlled voltage supply is obtained and the current driving capability of the design is increased, the hence less Gate leakage current is formed. This provides the motivation to explore the design of low leakage FinFET based Schmitt trigger. Simulation is performed on the cadence virtuoso tool in 45nm technology and simulation results revealed that there is a significant reduction in leakage current for this proposed design.