This paper is published in Volume-3, Issue-2, 2017
Area
VLSI
Author
Priyadharshini .M, Anitha .R, Saranya .P, Sindhu .M, Sindhu .K
Org/Univ
Sri Shakthi Institute Of Engineering and Technology, Coimbatore, Tamil Nadu, India
Pub. Date
11 March, 2017
Paper ID
V3I2-1198
Publisher
Keywords
Mtcmos, Dtcmos, Sleep Transistor, Leakage Current, Low Power, Leakage Reduction.

Citationsacebook

IEEE
Priyadharshini .M, Anitha .R, Saranya .P, Sindhu .M, Sindhu .K. Design & Optimization of Finfet Based Schmitt Trigger Using Leakage Reduction Techniques, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Priyadharshini .M, Anitha .R, Saranya .P, Sindhu .M, Sindhu .K (2017). Design & Optimization of Finfet Based Schmitt Trigger Using Leakage Reduction Techniques. International Journal of Advance Research, Ideas and Innovations in Technology, 3(2) www.IJARIIT.com.

MLA
Priyadharshini .M, Anitha .R, Saranya .P, Sindhu .M, Sindhu .K. "Design & Optimization of Finfet Based Schmitt Trigger Using Leakage Reduction Techniques." International Journal of Advance Research, Ideas and Innovations in Technology 3.2 (2017). www.IJARIIT.com.

Abstract

In this proposed work we are applying valuable power gating schemes to FinFET based Schmitt trigger to enhance its performance by reducing the leakage current in standby mode (off-state mode). The power gating schemes like Sleep Transistor approach and Multi-Threshold CMOS (MTCMOS) and Double-Threshold CMOS(DTCMOS) have been analysed and simulated which shows the tremendous reduction in the leakage current thus increasing the stability of the design. In this paper, different consecutive designs of PULL-UP and PULL-DOWN networks of NMOS and PMOS are applied to FinFET based Schmitt trigger one after another. Due to this treatment of PULL-UP and PULL-DOWN network, controlled voltage supply is obtained and the current driving capability of the design is increased, the hence less Gate leakage current is formed. This provides the motivation to explore the design of low leakage FinFET based Schmitt trigger. Simulation is performed on the cadence virtuoso tool in 45nm technology and simulation results revealed that there is a significant reduction in leakage current for this proposed design.
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