This paper is published in Volume-5, Issue-3, 2019
Area
Electronics and Communication Engineering
Author
Harsha R.
Co-authors
Anilkumar S. R., Chandan R., Jeevan Kumar S., Manjula N.
Org/Univ
Dr. Ambedkar Institute of Technology, Bengaluru, Karnataka, India
Pub. Date
14 May, 2019
Paper ID
V5I3-1340
Publisher
Keywords
Vedic mathematics, Urdhva Tiryagbhyam Sutra, Vedic multiplier, Adder, Transistors

Citationsacebook

IEEE
Harsha R., Anilkumar S. R., Chandan R., Jeevan Kumar S., Manjula N.. Design of Vedic multiplier using Urdhva Tiryagbhyam Sutra, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Harsha R., Anilkumar S. R., Chandan R., Jeevan Kumar S., Manjula N. (2019). Design of Vedic multiplier using Urdhva Tiryagbhyam Sutra. International Journal of Advance Research, Ideas and Innovations in Technology, 5(3) www.IJARIIT.com.

MLA
Harsha R., Anilkumar S. R., Chandan R., Jeevan Kumar S., Manjula N.. "Design of Vedic multiplier using Urdhva Tiryagbhyam Sutra." International Journal of Advance Research, Ideas and Innovations in Technology 5.3 (2019). www.IJARIIT.com.

Abstract

The multiplier is a key building block of all processors, which improves the speed of Digital Signal Processor (DSP), a special application in which we need to reduce the time delay. In the proposed method, we design a Vedic multiplier by using a Vedic Mathematics Sutra called Urdhva Tiryagbhyam, which means “vertically and crosswise”. Vedic Mathematics is mainly based on 16 Sutras and was rediscovered in the early 20th century. In ancient times in India, people used this Sutra for decimal number multiplications effectively. The same basic concept of the above-mentioned Sutra is extended to the multiplication of binary numbers to make use in the digital hardware system. The computation of partial products in parallel in the Urdhva Tiryagbhyam Sutra increases the speed of the computation process and the processing time is reduced in comparison with the use of inbuilt MATLAB functions. In our proposed multiplier design, the delay for the 4X4 Vedic multiplier is reduced and also the number of transistors is reduced by a large amount compared to the previously proposed design.
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