This paper is published in Volume-3, Issue-3, 2017
Area
VLSI
Author
Payal Gupta, Pankaj Gulhane
Org/Univ
Disha Institute Of Management And Technology, Raipur, Chhattisgarh, India
Keywords
CRC, HDLC, full duplex, FIFO, Flag Register.
Citations
IEEE
Payal Gupta, Pankaj Gulhane. Design and Implementation of HDLC Controller Using VHDL Code, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Payal Gupta, Pankaj Gulhane (2017). Design and Implementation of HDLC Controller Using VHDL Code. International Journal of Advance Research, Ideas and Innovations in Technology, 3(3) www.IJARIIT.com.
MLA
Payal Gupta, Pankaj Gulhane. "Design and Implementation of HDLC Controller Using VHDL Code." International Journal of Advance Research, Ideas and Innovations in Technology 3.3 (2017). www.IJARIIT.com.
Payal Gupta, Pankaj Gulhane. Design and Implementation of HDLC Controller Using VHDL Code, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.
APA
Payal Gupta, Pankaj Gulhane (2017). Design and Implementation of HDLC Controller Using VHDL Code. International Journal of Advance Research, Ideas and Innovations in Technology, 3(3) www.IJARIIT.com.
MLA
Payal Gupta, Pankaj Gulhane. "Design and Implementation of HDLC Controller Using VHDL Code." International Journal of Advance Research, Ideas and Innovations in Technology 3.3 (2017). www.IJARIIT.com.
Abstract
High Level Data Link Control (HDLC) is a bit oriented full duplex data link layer transceiver. HDLC controller has a Flag register with 8-bit pattern of 01111110 which generates the state of HDLC protocol. This paper describes the HDLC controller design using VHDL code consists of 16-bit cyclic redundancy checker (CRC) and FIFO. FIFO used for transmits the data. HDLC controller implement on Spartan 6 Xilinx FPGA.
