This paper is published in Volume-3, Issue-2, 2017
Area
Digital Electronics
Author
Priyanka Saraswat
Org/Univ
IEC College of Engineering and Technology, Uttar Pradesh, India
Pub. Date
14 April, 2017
Paper ID
V3I2-1505
Publisher
Keywords
RTL, ALU, ISE, Clock gating, Glitch.

Citationsacebook

IEEE
Priyanka Saraswat. A Review of Low Power Consumption Clock Gating Techniques, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Priyanka Saraswat (2017). A Review of Low Power Consumption Clock Gating Techniques. International Journal of Advance Research, Ideas and Innovations in Technology, 3(2) www.IJARIIT.com.

MLA
Priyanka Saraswat. "A Review of Low Power Consumption Clock Gating Techniques." International Journal of Advance Research, Ideas and Innovations in Technology 3.2 (2017). www.IJARIIT.com.

Abstract

This paper represents a review of some existing clock gating techniques for low power dissipation in digital circuitry designs. In this paper, the clock gating techniques are used which reduces the power consumption from the normal implementation of the same design. The 16 bit ALU (arithmetic logical unit) is used for reducing the dynamic power consumption through gating techniques by shutting down the clock at a given instant of time when it is not needed for work to prevent the unnecessary power consumption of the system. These designs are implemented on RTL level at VIVADO 2016.4 platform for synthesis and simulation by different gating techniques.
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