This paper is published in Volume-4, Issue-3, 2018
Area
VLSI
Author
T. Vamshi Krishna
Co-authors
Niveditha S, Mamatha. G. N, Sunil. M. P
Org/Univ
School of Engineering and Technology, Jain University, Bangalore Rural, Karnataka, India
Pub. Date
14 May, 2018
Paper ID
V4I3-1383
Publisher
Keywords
Brent Kung Adder, Delay, Parallel Prefix Adder and Power.

Citationsacebook

IEEE
T. Vamshi Krishna, Niveditha S, Mamatha. G. N, Sunil. M. P. Simulation study of brent kung adder using cadence tool, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
T. Vamshi Krishna, Niveditha S, Mamatha. G. N, Sunil. M. P (2018). Simulation study of brent kung adder using cadence tool. International Journal of Advance Research, Ideas and Innovations in Technology, 4(3) www.IJARIIT.com.

MLA
T. Vamshi Krishna, Niveditha S, Mamatha. G. N, Sunil. M. P. "Simulation study of brent kung adder using cadence tool." International Journal of Advance Research, Ideas and Innovations in Technology 4.3 (2018). www.IJARIIT.com.

Abstract

Adders are the most fundamental piece of any computerized framework. In order to perform the addition of two numbers, adders are used. They also form the requisite part of Arithmetic and Logic Unit. Besides this application, they are also used in computers to calculate address, indices and operation codes. Adders are also used to employ different algorithms in Digital Signal Processing. There is a prerequisite to provide an efficient adder design which fulfills the trade-off amongst speed and space consideration to increase the performance of the system. In the modern age, in addition to the trade-off between speed and space, power consumption assumes an imperative. Gadgets with low power utilization and good performance are favored in real-time applications. Parallel Prefix adders are the ones generally utilized as a part of Digital Designs due to the adaptability associated with outlining these Adders. Brent Kung Adder (BKA) is a low power parallel prefix adder, as it uses minimum circuitry to obtain the result. A simulation study of this adder is carried out using cadence tool. The 4-bit, 8-bit, 16-bit and 32-bit BKAs were designed and simulated using CMOS logic- 45nm Technology. A comparative study was made by comparing the obtained results with Ripple Carry adder and Carry Look-ahead adders. Obtained results show that the power consumption and propagation delay for the BKA implementation are reduced compared to RCA and CLA.
Paper PDF