This paper is published in Volume-6, Issue-2, 2020
Area
Electronics and Communication Engineering
Author
Nafies
Co-authors
Jenith K., Gowtham I. R., Arun Samuel T. S.
Org/Univ
National Engineering College, Kovilpatti, Tamil Nadu, India
Pub. Date
26 March, 2020
Paper ID
V6I2-1251
Publisher
Keywords
Cadence, CMOS, CPL, Full adder, Power consumption, Transistor, Transmission gates.

Citationsacebook

IEEE
Nafies, Jenith K., Gowtham I. R., Arun Samuel T. S.. Performance analysis of low power 1-Bit CMOS full adder, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Nafies, Jenith K., Gowtham I. R., Arun Samuel T. S. (2020). Performance analysis of low power 1-Bit CMOS full adder. International Journal of Advance Research, Ideas and Innovations in Technology, 6(2) www.IJARIIT.com.

MLA
Nafies, Jenith K., Gowtham I. R., Arun Samuel T. S.. "Performance analysis of low power 1-Bit CMOS full adder." International Journal of Advance Research, Ideas and Innovations in Technology 6.2 (2020). www.IJARIIT.com.

Abstract

One-bit full-adder efficiency and interpretation are anatomized into smaller parts. Such modules are thoroughly tested. Multiple designs are created, simulated and evaluated for each full adder. Twenty separate 1-bit full-adder modules are designed by integrating the various designs of these modules. Each of these full adder exhibits different power consumption, speed, area, and driving capabilities. Two realistic circuit structures that include full adders are used for simulation. The main aim of our project is to use CMOS technology to construct an optically reconfigurable low power full adder circuit. Analysis of time parameters in all existing full adders and comparison with the time study of our proposed circuit.
Paper PDF