This paper is published in Volume-4, Issue-3, 2018
Area
VLSI
Author
P. Aarthi
Co-authors
R. Suresh Kumar
Org/Univ
Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamil Nadu, India
Pub. Date
05 May, 2018
Paper ID
V4I3-1257
Publisher
Keywords
CMOS, Logic gates, Transmission gates, Pass topology.

Citationsacebook

IEEE
P. Aarthi, R. Suresh Kumar. Implementation of pull-up/pull-down network for energy optimization in full adder circuit, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
P. Aarthi, R. Suresh Kumar (2018). Implementation of pull-up/pull-down network for energy optimization in full adder circuit. International Journal of Advance Research, Ideas and Innovations in Technology, 4(3) www.IJARIIT.com.

MLA
P. Aarthi, R. Suresh Kumar. "Implementation of pull-up/pull-down network for energy optimization in full adder circuit." International Journal of Advance Research, Ideas and Innovations in Technology 4.3 (2018). www.IJARIIT.com.

Abstract

Nowadays the requirements of energy-optimized low power circuits in higher-end applications such as communication, IoT, biomedical systems etc., there are several techniques used to implement energy optimization in low power circuits but the static power dissipation needs to improved such kind of circuits. The conventional topology has been implemented in basic logical gates but the delay and power much higher in each individual cell. Now we proposed an unbalanced pull-up and pull-down network in full adder circuit using symbols. These techniques were employed to reduce the static power dissipation and switching delay in each individual cell. The design was implemented in Cadence virtuoso TMSC 180nm CMOS technology and it’s obtaining the total power dissipation 5.128nW.The pull-up and pull-down network used to reduce the static power dissipation in full adder is used to improve the operating speed of each individual. For further improving the operating speed of the full adder is implemented with various gating technique like Body Biased Drain Gating, Body Biased Power Gating, Body Biased DHPH, and Body Biased DHPF those techniques are analyzed and its power and delay is obtained.