This paper is published in Volume-4, Issue-1, 2018
Area
VLSI Design
Author
B. Shubhaker
Co-authors
E. Amareswar
Org/Univ
St.Martin's Engineering College, Hyderabad, Telangana , India
Pub. Date
25 January, 2018
Paper ID
V4I1-1245
Publisher
Keywords
FPGA Kit, DSP, ALU, Multipliers.

Citationsacebook

IEEE
B. Shubhaker, E. Amareswar. High Speed Vedic Multiplier Design using FPGA, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
B. Shubhaker, E. Amareswar (2018). High Speed Vedic Multiplier Design using FPGA. International Journal of Advance Research, Ideas and Innovations in Technology, 4(1) www.IJARIIT.com.

MLA
B. Shubhaker, E. Amareswar. "High Speed Vedic Multiplier Design using FPGA." International Journal of Advance Research, Ideas and Innovations in Technology 4.1 (2018). www.IJARIIT.com.

Abstract

Vedic mathematics is an ancient system of mathematics, which was formulated by Sri Jagadguru Swami Bharati Krishna Tirthaji (1884 - 1960). After a research of eight years, he developed sixteen mathematical formulae from Atharvana Veda. The sutras (aphorisms) covered each and every topic of Mathematics such as Arithmetic, Algebra, Geometry and Trigonometry, Differential, Integral, etc.The word “Vedic” is derived from the word “Veda” which means the power house of all knowledge and divine. The proposed Vedic multiplier is based on the “Urdhava Triyagbhayam” sutra (algorithm). These Sutras have been traditionally used for the multiplication of two numbers in the decimal number system. It literally means “Vertically and crosswise”. Shift operation is not necessary because the partial product calculation will perform it in a single step, which in turn saves time.  16×16 Vedic multiplier is designed by using Urdhava Tiryakbhyam sutra and using rca adder .The 16 bit Vedic multiplier and array multiplier are designed by using Xilinx Spartan-3E FPGA.
Paper PDF