This paper is published in Volume-3, Issue-3, 2017
Area
VLSI
Author
Sojy Yacob, Anu C. Kunjachan
Org/Univ
Viswajyothi College of Engineering and Technology, Vazhakulam, P.O, Muvattupuzha, Ernakulam, Kerala, India
Pub. Date
28 June, 2017
Paper ID
V3I3-1601
Publisher
Keywords
BIST - Built In Self-Test, SEC-DED - Single Error Correction Double Error Detection, FPGA - Field Programmable Gate Array, BISR - Built In Self Repair, BIST - Built In Self-Test

Citationsacebook

IEEE
Sojy Yacob, Anu C. Kunjachan. FPGA Implementation of Built In Self Repair Technique for Hard & Soft Errors in Memories, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Sojy Yacob, Anu C. Kunjachan (2017). FPGA Implementation of Built In Self Repair Technique for Hard & Soft Errors in Memories. International Journal of Advance Research, Ideas and Innovations in Technology, 3(3) www.IJARIIT.com.

MLA
Sojy Yacob, Anu C. Kunjachan. "FPGA Implementation of Built In Self Repair Technique for Hard & Soft Errors in Memories." International Journal of Advance Research, Ideas and Innovations in Technology 3.3 (2017). www.IJARIIT.com.

Abstract

Anything that changes the normal operation can be defined as an error in a memory. They can be of two types: - Soft errors & Hard errors. Soft errors are caused by external elements (such as radiation environments, electrical noises etc.) outside of the designer's control. Hard errors are mainly due to manufacturing defects or due to unknown sources. Since an error in the memory can affect the whole system, error detection & correction techniques are important. Our objective is to detect and correct errors in offline stage and in field usage. During offline test stage, BIST (Built in Self-Test) module will check for the errors in the entire memory. If any fault is detected, SEC-DED (Single Error Correction Double Error Detection) module will be initiated to correct one error. If there exits more than one error, reconfiguration module will remap the faulty cells with the spare memory cells. During the field usage, if any error occurs, the controller will categorize the errors to three types and apply different techniques to correct them. The whole system is implemented in FPGA and simulation results are noted.