This paper is published in Volume-3, Issue-2, 2017
Area
VlSI
Author
Dhatchayani. K, Abinaya .R, Brunthvini .P, Deepa .S, Yamuna .S
Org/Univ
Sri Shakthi Institute of Engineering and Technology., India
Pub. Date
15 March, 2017
Paper ID
V3I2-1205
Publisher
Keywords
MPSoC, BIST, Shared Bus, Fault Detection, Quartus, Questasim.

Citationsacebook

IEEE
Dhatchayani. K, Abinaya .R, Brunthvini .P, Deepa .S, Yamuna .S. Design and Verification of MPSoC on FPGA with Built-in Self Test, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Dhatchayani. K, Abinaya .R, Brunthvini .P, Deepa .S, Yamuna .S (2017). Design and Verification of MPSoC on FPGA with Built-in Self Test. International Journal of Advance Research, Ideas and Innovations in Technology, 3(2) www.IJARIIT.com.

MLA
Dhatchayani. K, Abinaya .R, Brunthvini .P, Deepa .S, Yamuna .S. "Design and Verification of MPSoC on FPGA with Built-in Self Test." International Journal of Advance Research, Ideas and Innovations in Technology 3.2 (2017). www.IJARIIT.com.

Abstract

Multiple Processor System on Chip (MPSoC) which uses multiple processors mainly used in Embedded applications due to their high processing speed and low power consumption. This paper focuses on the design and implementation of MPSoC on FPGA. Multiple single processors are interconnected by shared bus. This paper also provides a technique to solve a major challenge of handling faults in its main components i.e. processors and interconnect with built in test structure on every processor. By using this testing structure the faults occurred in processing elements (PEs) during the communication between the master and slave can be identified automatically. The functionality is analyzed and verified using Questasim and Quartus tool. The output of the proposed model is compared with MPSoC architecture without a testing structure to estimate the functionality improvement.
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