This paper is published in Volume-4, Issue-3, 2018
Area
VLSI
Author
Shaik Suhana
Co-authors
Yarasi Thejsawini, P. Madhavi
Org/Univ
Geethanjali Institute of Science and Technology, Nellore, Andhra Pradesh, India
Pub. Date
03 May, 2018
Paper ID
V4I3-1219
Publisher
Keywords
CNFET, CMOS, VedicMultiplier, Urdhva tiryagbhyam.

Citationsacebook

IEEE
Shaik Suhana, Yarasi Thejsawini, P. Madhavi. Design and analysis of VLSI circuit’s speed using CNFET technology, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Shaik Suhana, Yarasi Thejsawini, P. Madhavi (2018). Design and analysis of VLSI circuit’s speed using CNFET technology. International Journal of Advance Research, Ideas and Innovations in Technology, 4(3) www.IJARIIT.com.

MLA
Shaik Suhana, Yarasi Thejsawini, P. Madhavi. "Design and analysis of VLSI circuit’s speed using CNFET technology." International Journal of Advance Research, Ideas and Innovations in Technology 4.3 (2018). www.IJARIIT.com.

Abstract

This paper presents the difference between the CNFET and CMOS technologies by using the design of an efficient 8×8 Vedic multiplier with Urdhva-Tiryagbhyam sutra. A carbon nanotube field-effect transistor (CNFET) uses either a single carbon nanotube or an array of carbon nanotubes as the channel material instead of bulk silicon in the traditional MOSFET structure. CNFETs show different characteristics compared to MOSFETs in their performances. The CNFET has many parameters such as operating voltage, number of tubes, pitch, nanotube diameter, dielectric constant, and contact materials which determine the digital circuit performance. This reduces the size of the chip but also cost and delay to a great extent. Here the comparison of CMOS technique with the proposed CNFET technique in terms of speed, power consumption, number of transistors, delay takes place.