This paper is published in Volume-4, Issue-1, 2018
Area
VLSI
Author
Shillu Elsa Thomas
Org/Univ
Musaliar College of Engineering and Technology, Pathanamthitta, Kerala, India
Pub. Date
15 January, 2018
Paper ID
V4I1-1203
Publisher
Keywords
2 Stage OP-AMP, CMOS, Gain, Phase Margin, Unity Gain Band Width.

Citationsacebook

IEEE
Shillu Elsa Thomas. Design of Flip-Flops for High Performance VLSI Applications Using Different CMOS Technology’s, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Shillu Elsa Thomas (2018). Design of Flip-Flops for High Performance VLSI Applications Using Different CMOS Technology’s. International Journal of Advance Research, Ideas and Innovations in Technology, 4(1) www.IJARIIT.com.

MLA
Shillu Elsa Thomas. "Design of Flip-Flops for High Performance VLSI Applications Using Different CMOS Technology’s." International Journal of Advance Research, Ideas and Innovations in Technology 4.1 (2018). www.IJARIIT.com.

Abstract

In this paper low power, high-speed design of SET, DET, TSPC and C2CMOS Flip-Flop are designed and analyzed. As these flip-flops have a small area and low power consumption they can be used in various applications like digital VLSI clocking system, buffers, registers, microprocessors etc. The Flip-Flops are analyzed at 90nm technologies. The above designed Flip-Flops and Latches are compared in terms of its transistor count, power dissipation and propagation delay using DSCH and Micro wind tools. This project proposes low power high-speed design of flip-flops in which True Single-Phase Clocking (TSPC) and C2CMOS flip-flop compared with existing flip-flop topologies in term of its transistor count, power dissipation, propagation delay, parasitic values with the simulation results in micro wind.
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