This paper is published in Volume-3, Issue-6, 2017
Area
ICT
Author
Dr. Tin Tin Nwet, Dr. Phyu Phyu Shein
Org/Univ
Computer University, Sittwe, Rakhine, Myanmar
Pub. Date
27 December, 2017
Paper ID
V3I6-1282
Publisher
Keywords
5681

Citationsacebook

IEEE
Dr. Tin Tin Nwet, Dr. Phyu Phyu Shein. Design and Implementation of Microprocessor Trainer Bus System, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Dr. Tin Tin Nwet, Dr. Phyu Phyu Shein (2017). Design and Implementation of Microprocessor Trainer Bus System. International Journal of Advance Research, Ideas and Innovations in Technology, 3(6) www.IJARIIT.com.

MLA
Dr. Tin Tin Nwet, Dr. Phyu Phyu Shein. "Design and Implementation of Microprocessor Trainer Bus System." International Journal of Advance Research, Ideas and Innovations in Technology 3.6 (2017). www.IJARIIT.com.

Abstract

This paper presents a part of a microprocessor trainer system. This paper has six modules. All modules are connected on the bus paths. Control signal such as Direct Memory Access (DMA), I/O Module and memory Modules are attached to the bus. In this paper, the bus has four lines of the bus. They are a line of the address, data, control (Memory Read/ Write and I/O Read/Write) and power. The address bus and data bus are 16 bits. Several Microcontrollers are in this paper. PIC 16f877 is used in a DMA module (direct memory access) and I/O module. PIC 74LS573 is applied as Latch, PIC74LS244 is used as a bus driver and PIC74LS255 is applied as a bus transceiver. PIC18f452 is used in CPU module. Each type of bus has its own requirements and properties.