This paper is published in Volume-4, Issue-5, 2018
Area
Electronics Engineering
Author
Nidhi Khanna
Co-authors
Renu Mehta, Dr. R. S. Gamad
Org/Univ
Shri Govindram Seksaria Institute of Technology and Science, Indore, Madhya Pradesh, India
Pub. Date
26 September, 2018
Paper ID
V4I5-1254
Publisher
Keywords
Low power, Sequential circuits, Flip-flop, Counter, FPGA

Citationsacebook

IEEE
Nidhi Khanna, Renu Mehta, Dr. R. S. Gamad. Low power design of 4-bits counter at circuit and system level of abstraction, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Nidhi Khanna, Renu Mehta, Dr. R. S. Gamad (2018). Low power design of 4-bits counter at circuit and system level of abstraction. International Journal of Advance Research, Ideas and Innovations in Technology, 4(5) www.IJARIIT.com.

MLA
Nidhi Khanna, Renu Mehta, Dr. R. S. Gamad. "Low power design of 4-bits counter at circuit and system level of abstraction." International Journal of Advance Research, Ideas and Innovations in Technology 4.5 (2018). www.IJARIIT.com.

Abstract

This paper presents a design of Low power 4 bits Counter at circuit and system level of abstraction using Cadence Virtuoso and Xilinx ISE 14.7 respectively. The laboratory work described includes the CMOS based transistor level design and VHDL based synthesis and implementation of the counter using back end and front end tools respectively. The functionality of the design has been simulated and tested using 0.18µm gdpk CMOS technology with 1.8V supply voltage using cadence virtuoso for back-end designing whereas, Xilinx ISE 14.7 is used for front-end simulation, synthesized using plan¬-ahead and is implemented on ArtixTM-7(family), with device xC7A100TTM. Power calculation has been done at 100 MHz clock frequency for the 1.8V supply voltage.