This paper is published in Volume-4, Issue-3, 2018
Area
VLSI
Author
Kaleeswari. S
Co-authors
Saranya. K
Org/Univ
Tejaa Shakthi Institute of Technology for Women, Coimbatore, Tamil Nadu, India
Pub. Date
05 May, 2018
Paper ID
V4I3-1258
Publisher
Keywords
CMOS. Transmission gate, Pass transistor logic, Adder.

Citationsacebook

IEEE
Kaleeswari. S, Saranya. K. Efficient implementation of full adder and multiplier for power analysis in CMOS technology, International Journal of Advance Research, Ideas and Innovations in Technology, www.IJARIIT.com.

APA
Kaleeswari. S, Saranya. K (2018). Efficient implementation of full adder and multiplier for power analysis in CMOS technology. International Journal of Advance Research, Ideas and Innovations in Technology, 4(3) www.IJARIIT.com.

MLA
Kaleeswari. S, Saranya. K. "Efficient implementation of full adder and multiplier for power analysis in CMOS technology." International Journal of Advance Research, Ideas and Innovations in Technology 4.3 (2018). www.IJARIIT.com.

Abstract

In recent days, the real-time application and fast arithmetic operations require highly efficient arithmetic hardware architecture to improve the system performances. The adder plays a vital role in digital circuits, the earlier hardware architecture using conventional CMOS and transmission logic gate based full adder design. Moreover, the techniques using more number of transistors and consume larger power and delay so we proposed the techniques pass-transistor logic and transmission gate based hybrid pass logic. The hybrid technique is used to reduce the number of the transistor, so the delay and power consumption will be reduced when compared with the earlier techniques. The proposed technique design was implemented using 16 transistors in 180nm CMOS technology and it consumes 8.2075nW power and the delay reduced to 5.0146ns. For further improving the power and delay will be minimized using analog multiplier technique which is implemented in 180nm CMOS technology and it consumes 3.2993 MW power and 1.2884 ms.